NK

Navneet Kaushik

CS Cadence Design Systems: 2 patents #20 of 223Top 9%
Overall (2018): #116,897 of 503,207Top 25%
2
Patents 2018

Issued Patents 2018

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10095822 Memory built-in self-test logic in an integrated circuit design Puneet Arora, Steven Lee Gregor, Norman Robert Card 2018-10-09
9865362 Method and apparatus for testing error correction code (ECC) logic and physical memory onboard a manufactured integrated circuit (IC) Puneet Arora, Steven Lee Gregor, Norman Robert Card 2018-01-09