NC

Norman Robert Card

CS Cadence Design Systems: 3 patents #4 of 223Top 2%
📍 Vestal, NY: #7 of 41 inventorsTop 20%
🗺 New York: #1,509 of 11,825 inventorsTop 15%
Overall (2018): #62,459 of 503,207Top 15%
3
Patents 2018

Issued Patents 2018

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
10095822 Memory built-in self-test logic in an integrated circuit design Navneet Kaushik, Puneet Arora, Steven Lee Gregor 2018-10-09
10007489 Automated method identifying physical memories within a core or macro integrated circuit design Puneet Arora, Steven Lee Gregor 2018-06-26
9865362 Method and apparatus for testing error correction code (ECC) logic and physical memory onboard a manufactured integrated circuit (IC) Puneet Arora, Steven Lee Gregor, Navneet Kaushik 2018-01-09