Issued Patents 2017
Showing 1–25 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9836609 | Event-based apparatus and method for securing bios in a trusted computing system during execution | — | 2017-12-05 |
| 9836610 | Event-based apparatus and method for securing BIOS in a trusted computing system during execution | — | 2017-12-05 |
| 9830155 | Microprocessor using compressed and uncompressed microcode storage | Terry Parks, Brent Bean | 2017-11-28 |
| 9829945 | Power management synchronization messaging system | Darius D. Gaskins | 2017-11-28 |
| 9811344 | Core ID designation system for dynamically designated bootstrap processor | Stephan Gaskins | 2017-11-07 |
| 9805198 | Event-based apparatus and method for securing bios in a trusted computing system during execution | — | 2017-10-31 |
| 9804845 | Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor | Gerard M. Col, Colin Eddy | 2017-10-31 |
| 9798880 | Fuse-enabled secure bios mechanism with override feature | — | 2017-10-24 |
| 9798898 | Microprocessor with secure execution mode and store key instructions | Terry Parks, Brent Bean, Thomas A. Crispin | 2017-10-24 |
| 9792121 | Microprocessor that fuses if-then instructions | Terry Parks | 2017-10-17 |
| 9792112 | Propagation of microcode patches to multiple cores in multicore microprocessor | Stephan Gaskins | 2017-10-17 |
| 9779243 | Fuse-enabled secure BIOS mechanism in a trusted computing system | — | 2017-10-03 |
| 9779242 | Programmable secure bios mechanism in a trusted computing system | — | 2017-10-03 |
| 9767288 | JTAG-based secure BIOS mechanism in a trusted computing system | — | 2017-09-19 |
| 9768803 | Hardware data compressor using dynamic hash algorithm based on input block type | Terry Parks | 2017-09-19 |
| 9740622 | Extended fuse reprogrammability mechanism | Dinesh K. Jain | 2017-08-22 |
| 9740271 | Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor | Gerard M. Col, Colin Eddy | 2017-08-22 |
| 9727477 | Core-specific fuse mechanism for a multi-core die | Dinesh K. Jain | 2017-08-08 |
| 9727478 | Apparatus and method for configurable redundant fuse banks | Dinesh K. Jain | 2017-08-08 |
| 9715457 | Multi-core fuse decompression mechanism | Dinesh K. Jain | 2017-07-25 |
| 9715456 | Apparatus and method for storage and decompression of configuration data | Dinesh K. Jain | 2017-07-25 |
| 9710390 | Apparatus and method for extended cache correction | Dinesh K. Jain | 2017-07-18 |
| 9703359 | Power saving mechanism to reduce load replays in out-of-order processor | Gerard M. Col, Colin Eddy | 2017-07-11 |
| 9690511 | Multi-core data array power gating restoral mechanism | Dinesh K. Jain, Stephan Gaskins | 2017-06-27 |
| 9665490 | Apparatus and method for repairing cache arrays in a multi-core microprocessor | Dinesh K. Jain, Stephan Gaskins | 2017-05-30 |