GH

G. Glenn Henry

VC Via Alliance Semiconductor Co.: 21 patents #1 of 62Top 2%
VT Via Technologies: 18 patents #1 of 40Top 3%
🗺 Texas: #4 of 15,389 inventorsTop 1%
Overall (2017): #336 of 506,227Top 1%
39
Patents 2017

Issued Patents 2017

Showing 26–39 of 39 patents

Patent #TitleCo-InventorsDate
9645822 Conditional store instructions in an out-of-order execution microprocessor Terry Parks, Rodney E. Hooker, Gerard M. Col, Colin Eddy 2017-05-09
9645827 Mechanism to preclude load replays dependent on page walks in an out-of-order processor Gerard M. Col, Colin Eddy 2017-05-09
9628111 Hardware data compressor with multiple string match search hash tables each based on different hash size Terry Parks 2017-04-18
9606933 Multi-core apparatus and method for restoring data arrays following a power gating event Dinesh K. Jain, Stephan Gaskins 2017-03-28
9594691 Multi-core programming apparatus and method for restoring data arrays following a power gating event Dinesh K. Jain, Stephan Gaskins 2017-03-14
9594690 Multi-core microprocessor power gating cache restoral programming mechanism Dinesh K. Jain, Stephan Gaskins 2017-03-14
9588845 Processor that recovers from excessive approximate computing error Terry Parks, Rodney E. Hooker 2017-03-07
9588572 Multi-core processor having control unit that generates interrupt requests to all cores in response to synchronization condition Terry Parks 2017-03-07
9582429 Multi-core data array power gating cache restoral programming mechanism Dinesh K. Jain, Stephan Gaskins 2017-02-28
9582428 Multi-core programming apparatus and method for restoring data arrays following a power gating event Dinesh K. Jain, Stephan Gaskins 2017-02-28
9575541 Propagation of updates to per-core-instantiated architecturally-visible storage resource Stephan Gaskins 2017-02-21
9547767 Event-based apparatus and method for securing bios in a trusted computing system during execution 2017-01-17
9535847 Apparatus and method for compression of configuration data Dinesh K. Jain 2017-01-03
9535488 Multi-core microprocessor that dynamically designates one of its processing cores as the bootstrap processor Stephan Gaskins 2017-01-03