| 9830155 |
Microprocessor using compressed and uncompressed microcode storage |
G. Glenn Henry, Brent Bean |
2017-11-28 |
| 9798898 |
Microprocessor with secure execution mode and store key instructions |
G. Glenn Henry, Brent Bean, Thomas A. Crispin |
2017-10-24 |
| 9792223 |
Processor including load EPT instruction |
Colin Eddy |
2017-10-17 |
| 9792121 |
Microprocessor that fuses if-then instructions |
G. Glenn Henry |
2017-10-17 |
| 9768803 |
Hardware data compressor using dynamic hash algorithm based on input block type |
G. Glenn Henry |
2017-09-19 |
| 9759368 |
Multipurpose lighting and entertainment stand |
Esther Parks |
2017-09-12 |
| 9727480 |
Efficient address translation caching in a processor that supports a large number of different address spaces |
Colin Eddy, Viswanath Mohan, John Bunda |
2017-08-08 |
| 9652398 |
Cache replacement policy that considers memory access type |
Rodney E. Hooker, Douglas R. Reed, John Michael Greer, Colin Eddy |
2017-05-16 |
| 9645822 |
Conditional store instructions in an out-of-order execution microprocessor |
G. Glenn Henry, Rodney E. Hooker, Gerard M. Col, Colin Eddy |
2017-05-09 |
| 9628111 |
Hardware data compressor with multiple string match search hash tables each based on different hash size |
G. Glenn Henry |
2017-04-18 |
| 9588572 |
Multi-core processor having control unit that generates interrupt requests to all cores in response to synchronization condition |
G. Glenn Henry |
2017-03-07 |
| 9588845 |
Processor that recovers from excessive approximate computing error |
G. Glenn Henry, Rodney E. Hooker |
2017-03-07 |