Issued Patents 2017
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date | Approx Value ⓘ |
|---|---|---|---|---|
| 9785046 | Pattern verifying method | Te-Hsien Hsieh, Cheng-Te Wang, Jing-Yi Lee, Jian-Yuan Ma, Yan-Chun Chen | 2017-10-10 | $217,000 |
| 9747404 | Method for optimizing an integrated circuit layout design | Shih-Ming Kuo, Te-Hsien Hsieh, Ping-I Hsieh, Jing-Yi Lee, Yan-Chun Chen | 2017-08-29 | $143,000 |
| 9673145 | Semiconductor integrated circuit layout structure | Shih-Chin Lin, Kuei-Chun Hung, Jerry Hu, Chen-Hsien Hsu | 2017-06-06 | $174,000 |
| 9653346 | Integrated FinFET structure having a contact plug pitch larger than fin and first metal pitch | Shih-Chin Lin, Kuei-Chun Hung, Jerry Hu, Chen-Hsien Hsu | 2017-05-16 | $134,000 |
| 9627036 | Static random access memory layout structure | Tan-Ya Yin, Chia-Wei Huang, Yu-Cheng Tung, Chin-Sheng Yang | 2017-04-18 | $94,000 |
| 9613969 | Semiconductor structure and method of forming the same | Ching-Wen Hung, Wei-Cyuan Lo, Chia-Lin Lu, Jia-Rong Wu, Yi-Hui Lee +8 more | 2017-04-04 | $147,000 |