Issued Patents 2017
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9837348 | Voids in interconnect structures and methods for forming the same | Jiun-Jie Huang | 2017-12-05 |
| 9831314 | Surface profile for semiconductor region | Chao-Hsuing Chen, Chi-Yen Lin | 2017-11-28 |
| 9818704 | Stress tuning for reducing wafer warpage | Yung-Yao Wang, Ying-Han Chiou | 2017-11-14 |
| 9735252 | V-shaped SiGe recess volume trim for improved device performance and layout dependence | Chao-Hsuing Chen, Chi-Yen Lin | 2017-08-15 |
| 9722082 | Methods and apparatus for doped SiGe source/drain stressor deposition | Chao-Hsuing Chen, Chi-Yen Lin | 2017-08-01 |
| 9634122 | Device boost by quasi-FinFET | Ru-Shang Hsiao, Chih-Mu Huang, Chia-Ming Chang | 2017-04-25 |
| 9564487 | Dual vertical channel | Ru-Shang Hsiao, Chia-Ming Chang, Huang Jiun-Jie | 2017-02-07 |
| 9543399 | Device having sloped gate profile and method of manufacture | Ru-Shang Hsiao, Chih-Mu Huang, Yao-Tsung Chen, Ming-Tsang Tsai, Kuan-Yu Chen | 2017-01-10 |