Issued Patents 2017
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9824013 | Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors | Christopher Edward Koob, Ajay Anant Ingle, Lucian Codrescu | 2017-11-21 |
| 9804969 | Speculative addressing using a virtual address-to-physical address page crossing buffer | Jiajin Tu, Phillip M. Jones | 2017-10-31 |
| 9715392 | Multiple clustered very long instruction word processing core | Ankit Ghiya, Peter G. Sassone, Lucian Codrescu, Suman Mamidi | 2017-07-25 |
| 9678754 | System and method of processing hierarchical very long instruction packets | Lucian Codrescu, Erich James Plondke, Ajay Anant Ingle, Charles Joseph Tabony | 2017-06-13 |
| 9678758 | Coprocessor for out-of-order loads | Lucian Codrescu, Christopher Edward Koob, Eric W. Mahurin | 2017-06-13 |
| 9552033 | Latency-based power mode units for controlling power modes of processor cores, and related methods and systems | Peter G. Sassone, Sanjay Bhagawan Patil | 2017-01-24 |