Issued Patents 2017
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9824013 | Per thread cacheline allocation mechanism in shared partitioned caches in multi-threaded processors | Ajay Anant Ingle, Lucian Codrescu, Suresh K. Venkumahanti | 2017-11-21 |
| 9785211 | Independent power collapse methodology | Xufeng Chen, Robert A. Lester, Manojkumar Pyla, Peixin Zhong | 2017-10-10 |
| 9767025 | Write-only dataless state for maintaining cache coherency | Dana Michelle Vantrease | 2017-09-19 |
| 9678758 | Coprocessor for out-of-order loads | Lucian Codrescu, Eric W. Mahurin, Suresh K. Venkumahanti | 2017-06-13 |
| 9658793 | Adaptive mode translation lookaside buffer search and access fault | Erich James Plondke, Jiajin Tu | 2017-05-23 |
| 9606818 | Systems and methods of executing multiple hypervisors using multiple sets of processors | Erich James Plondke, Lucian Codrescu, Piyush Patel, Thomas Andrew Sartorius | 2017-03-28 |