Issued Patents 2017
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9667237 | Hardware delay compensation in digital phase locked loop | Qu Gary Jin, Krste Mitric, Cathy Zhang, Gabriel Rusaneanu, Wenbao Wang | 2017-05-30 |
| 9647674 | Apparatus for generating clock signals having a PLL part and synthesizer part with programmable output dividers | Krste Mitric, Gabriel Rusaneanu | 2017-05-09 |
| 9634675 | Phase locked loop with jump-free holdover mode | Krste Mitric | 2017-04-25 |
| 9595972 | Digital phase locked loop arrangement with master clock redundancy | Slobodan Milijevic, Johannes Hermanus Aloysius de Rijk, Mark A Warriner | 2017-03-14 |
| 9584138 | Phase locked loop with accurate alignment among output clocks | Krste Mitric, Qu Gary Jin, Guohui Situ, Changhui Zhang, Richard Geiss | 2017-02-28 |