Issued Patents 2017
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9595972 | Digital phase locked loop arrangement with master clock redundancy | Johannes Hermanus Aloysius de Rijk, Paul H. L. M. Schram, Mark A Warriner | 2017-03-14 |
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9595972 | Digital phase locked loop arrangement with master clock redundancy | Johannes Hermanus Aloysius de Rijk, Paul H. L. M. Schram, Mark A Warriner | 2017-03-14 |