Issued Patents 2017
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9726691 | 3D chip testing through micro-C4 interface | Victor A. Garibay, Chetan Mehta, Doorlabh Panjwani | 2017-08-08 |
| 9646925 | Interconnect array pattern with a 3:1 signal-to-ground ratio | Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar | 2017-05-09 |
| 9600619 | Distribution of power vias in a multi-layer circuit board | Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar | 2017-03-21 |
| 9594865 | Distribution of power vias in a multi-layer circuit board | Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar | 2017-03-14 |
| 9543241 | Interconnect array pattern with a 3:1 signal-to-ground ratio | Zhaoqing Chen, Matteo Cocchini, Rohan U. Mandrekar | 2017-01-10 |