Issued Patents 2017
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9773725 | Coreless multi-layer circuit substrate with minimized pad capacitance | Kevin Bills, Mahesh Bohra, Jinwoo Choi, Tae Hong Kim | 2017-09-26 |
| 9646925 | Interconnect array pattern with a 3:1 signal-to-ground ratio | Zhaoqing Chen, Matteo Cocchini, Tingdong Zhou | 2017-05-09 |
| 9600619 | Distribution of power vias in a multi-layer circuit board | Zhaoqing Chen, Matteo Cocchini, Tingdong Zhou | 2017-03-21 |
| 9594865 | Distribution of power vias in a multi-layer circuit board | Zhaoqing Chen, Matteo Cocchini, Tingdong Zhou | 2017-03-14 |
| 9543241 | Interconnect array pattern with a 3:1 signal-to-ground ratio | Zhaoqing Chen, Matteo Cocchini, Tingdong Zhou | 2017-01-10 |