Issued Patents 2017
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9831135 | Method of forming a biCMOS semiconductor chip that increases the betas of the bipolar transistors | Natalia Lavrovskaya, Andrew Strachan | 2017-11-28 |
| 9786665 | Dual deep trenches for high voltage isolation | Sameer Pendharkar, Binghua Hu, Guru Mathur | 2017-10-10 |
| 9773777 | Low dynamic resistance low capacitance diodes | Andrew Strachan, Gang Xue, Dening Wang | 2017-09-26 |
| 9741790 | Method for creating the high voltage complementary BJT with lateral collector on bulk substrate with resurf effect | Jeffrey A. Babcock | 2017-08-22 |
| 9640611 | HV complementary bipolar transistors with lateral collectors on SOI with resurf regions under buried oxide | Jeffrey A. Babcock | 2017-05-02 |
| 9633995 | Method of forming a gate shield in an ED-CMOS transistor and a base of a bipolar transistor using BICMOS technologies | Jeffrey A. Babcock | 2017-04-25 |
| 9633994 | BICMOS device having commonly defined gate shield in an ED-CMOS transistor and base in a bipolar transistor | Jeffrey A. Babcock | 2017-04-25 |
| 9595480 | Method of forming a BICMOS semiconductor chip that increases the betas of the bipolar transistors | Natalia Lavrovskaya, Andrew Strachan | 2017-03-14 |