Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
JD

Joseph Doller

Intel: 1 patents #2,217 of 5,604Top 40%
Park Village, CA: #16 of 24 inventorsTop 70%
California: #24,257 of 60,394 inventorsTop 45%
Overall (2017): #370,896 of 506,227Top 75%
1 Patents 2017

Issued Patents 2017

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
9679658 Method and apparatus for reducing read latency for a block erasable non-volatile memory David J. Pelster, Yogesh B. Wakchaure, Xin Guo, Paul D. Ruby, Justin R. Dayacap +1 more 2017-06-13