Issued Patents 2017
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9852245 | Dynamic fault model generation for diagnostics simulation and pattern generation | Gary W. Maier, Franco Motika, Phong T. Tran | 2017-12-26 |
| 9746516 | Collecting diagnostic data from chips | Steven M. Douskey, Ryan A. Fitch, William V. Huott | 2017-08-29 |
| 9689920 | Identification of unknown sources for logic built-in self test in verification | Satya R. S. Bhamidipati, Cedric Lichtenau, Srinivas V. N. Polisetty | 2017-06-27 |
| 9651623 | Reducing power requirements and switching during logic built-in-self-test and scan test | Satya R. S. Bhamidipati, Cedric Lichtenau | 2017-05-16 |
| 9651616 | Reducing power requirements and switching during logic built-in-self-test and scan test | Satya R. S. Bhamidipati, Cedric Lichtenau | 2017-05-16 |
| 9588177 | Optimizing generation of test configurations for built-in self-testing | Eugene Atwood, Paul Jacob Logsdon, Franco Motika, Andrew A. Turner | 2017-03-07 |
| 9557381 | Physically aware insertion of diagnostic circuit elements | William V. Huott, Sridhar H. Rangarajan, Robert C. Redburn, Andrew A. Turner | 2017-01-31 |
| 9552449 | Dynamic fault model generation for diagnostics simulation and pattern generation | Gary W. Maier, Franco Motika, Phong T. Tran | 2017-01-24 |