Issued Patents 2017
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9836399 | Mechanism to avoid hot-L1/cold-L2 events in an inclusive L2 cache using L1 presence bits for victim selection bias | Krishna N. Vinod, Zainulabedin J. Aurangabadwala | 2017-12-05 |
| 9733939 | Physical reference list for tracking physical register sharing | Vijaykumar B. Kadgi, James Hadley, Matthew C. Merten, Morris Marden, Joseph A. McMahon +4 more | 2017-08-15 |
| 9720827 | Providing multiple memory modes for a processor including internal memory | Robert J. Kyanko, Richard J. Greco, Andreas Kleen, Milind B. Girkar, Christopher M. Cantalupo | 2017-08-01 |
| 9594648 | Controlling non-redundant execution in a redundant multithreading (RMT) processor | Glenn J. Hinton, Steven Raasch, Sebastien Hily, John G. Holm, Ronak Singhal +1 more | 2017-03-14 |