MO

Meir Ovadia

CS Cadence Design Systems: 4 patents #4 of 238Top 2%
Overall (2017): #41,599 of 506,227Top 9%
4
Patents 2017

Issued Patents 2017

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
9852046 Method and system for automated debugging memory allocation and memory release Rodion Melnikov, Yonatan Ashkenazi 2017-12-26
9823305 Method and system for generating post-silicon validation tests Swaminathan Venkateasan 2017-11-21
9792402 Method and system for debugging a system on chip under test Kalev Alpernas 2017-10-17
9690681 Method and system for automatically generating executable system-level tests Erez Singer, Efrat Gavish 2017-06-27