SV

Swaminathan Venkateasan

CS Cadence Design Systems: 1 patents #55 of 238Top 25%
📍 Irvine, CA: #398 of 1,054 inventorsTop 40%
🗺 California: #24,257 of 60,394 inventorsTop 45%
Overall (2017): #505,162 of 506,227Top 100%
1
Patents 2017

Issued Patents 2017

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
9823305 Method and system for generating post-silicon validation tests Meir Ovadia 2017-11-21