KA

Kalev Alpernas

CS Cadence Design Systems: 1 patents #55 of 238Top 25%
📍 Lod, IL: #17 of 48 inventorsTop 40%
Overall (2017): #356,796 of 506,227Top 75%
1
Patents 2017

Issued Patents 2017

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
9792402 Method and system for debugging a system on chip under test Meir Ovadia 2017-10-17