| 9489314 |
Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC |
Kai Chirca, Timothy David Anderson |
2016-11-08 |
| 9465767 |
Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect |
Kai Chirca, Daniel Wu, Timothy David Anderson |
2016-10-11 |
| 9465741 |
Multi processor multi domain conversion bridge with out of order return buffering |
Kai Chirca, Daniel Wu, Timothy David Anderson |
2016-10-11 |
| 9424193 |
Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems |
Kai Chirca |
2016-08-23 |
| 9372799 |
Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion |
Daniel Wu, Kai Chirca, Timothy David Anderson |
2016-06-21 |
| 9372796 |
Optimum cache access scheme for multi endpoint atomic access in a multicore system |
Kai Chirca |
2016-06-21 |
| 9372808 |
Deadlock-avoiding coherent system on chip interconnect |
Daniel Wu, Kai Chirca |
2016-06-21 |
| 9304954 |
Multi processor bridge with mixed Endian mode support |
Daniel Wu, Kai Chirca |
2016-04-05 |
| 9304925 |
Distributed data return buffer for coherence system with speculative address support |
Kai Chirca |
2016-04-05 |
| 9298665 |
Multicore, multibank, fully concurrent coherence controller |
Kai Chirca |
2016-03-29 |
| 9239798 |
Prefetcher with arbitrary downstream prefetch cancelation |
Joseph Zbiciak, Kai Chirca, Amitabh Menon, Timothy David Anderson |
2016-01-19 |