| 9489307 |
Multi domain bridge with auto snoop response |
Timothy David Anderson |
2016-11-08 |
| 9465741 |
Multi processor multi domain conversion bridge with out of order return buffering |
Kai Chirca, Matthew D. Pierson, Timothy David Anderson |
2016-10-11 |
| 9465742 |
Synchronizing barrier support with zero performance impact |
Kai Chirca |
2016-10-11 |
| 9465767 |
Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect |
Kai Chirca, Matthew D. Pierson, Timothy David Anderson |
2016-10-11 |
| 9372799 |
Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion |
Matthew D. Pierson, Kai Chirca, Timothy David Anderson |
2016-06-21 |
| 9372808 |
Deadlock-avoiding coherent system on chip interconnect |
Matthew D. Pierson, Kai Chirca |
2016-06-21 |
| 9304954 |
Multi processor bridge with mixed Endian mode support |
Matthew D. Pierson, Kai Chirca |
2016-04-05 |