| 9489314 |
Multi-master cache coherent speculation aware memory controller with advanced arbitration, virtualization and EDC |
Matthew D. Pierson, Timothy David Anderson |
2016-11-08 |
| 9465741 |
Multi processor multi domain conversion bridge with out of order return buffering |
Daniel Wu, Matthew D. Pierson, Timothy David Anderson |
2016-10-11 |
| 9465742 |
Synchronizing barrier support with zero performance impact |
Daniel Wu |
2016-10-11 |
| 9465767 |
Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect |
Matthew D. Pierson, Daniel Wu, Timothy David Anderson |
2016-10-11 |
| 9448767 |
Three-term predictive adder and/or subtracter |
Timothy David Anderson, Mujibur Rahman |
2016-09-20 |
| 9424193 |
Flexible arbitration scheme for multi endpoint atomic accesses in multicore systems |
Matthew D. Pierson |
2016-08-23 |
| 9372808 |
Deadlock-avoiding coherent system on chip interconnect |
Matthew D. Pierson, Daniel Wu |
2016-06-21 |
| 9372796 |
Optimum cache access scheme for multi endpoint atomic access in a multicore system |
Matthew D. Pierson |
2016-06-21 |
| 9372799 |
Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion |
Daniel Wu, Matthew D. Pierson, Timothy David Anderson |
2016-06-21 |
| 9304954 |
Multi processor bridge with mixed Endian mode support |
Daniel Wu, Matthew D. Pierson |
2016-04-05 |
| 9304925 |
Distributed data return buffer for coherence system with speculative address support |
Matthew D. Pierson |
2016-04-05 |
| 9298665 |
Multicore, multibank, fully concurrent coherence controller |
Matthew D. Pierson |
2016-03-29 |
| 9239798 |
Prefetcher with arbitrary downstream prefetch cancelation |
Matthew D. Pierson, Joseph Zbiciak, Amitabh Menon, Timothy David Anderson |
2016-01-19 |