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Reduced refresh power |
Frederick A. Ware, Brent Haukness, Gary B. Bronner |
2016-11-08 |
| 9479176 |
Methods and circuits for protecting integrated circuits from reverse engineering |
John Eble, Hanson Quan |
2016-10-25 |
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Methods and apparatus for synchronizing communication with a memory controller |
Richard E. Warmke, David B. Roberts, Frank Lambrecht |
2016-10-11 |
| 9450614 |
Memory module with integrated error correction |
Frederick A. Ware |
2016-09-20 |
| 9412428 |
Memory components and controllers that calibrate multiphase synchronous timing references |
Thomas J. Giovannini, Lei Luo, Ian Shaeffer |
2016-08-09 |
| 9390782 |
Memory with refresh logic to accommodate low-retention storage rows |
Ely Tsern |
2016-07-12 |
| 9384152 |
Coordinating memory operations using memory-device generated reference signals |
Ian Shaeffer |
2016-07-05 |
| 9324411 |
Multi-die memory device |
Ming Li |
2016-04-26 |
| 9256376 |
Methods and circuits for dynamically scaling DRAM power and performance |
Ely Tsern, Thomas Vogelsang, Craig E. Hampel |
2016-02-09 |
| 9231731 |
Common mode calibration |
Huy M. Nguyen, Kambiz Kaviani, Reza Navid, Jason C. Wei, Xudong Shi |
2016-01-05 |