Issued Patents 2016
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9501847 | Parallel line stipple computation | Timothy John Purcell | 2016-11-22 |
| 9483270 | Distributed tiled caching | Cynthia Ann Edgeworth Allison, Dale L. Kirkland, Walter R. Steiner | 2016-11-01 |
| 9478066 | Consistent vertex snapping for variable resolution rendering | Eric B. Lum, Henry Packard Moreton, Kyle Perry Roden, Walter R. Steiner | 2016-10-25 |
| 9448804 | Techniques for managing graphics processing resources in a tile-based architecture | Cynthia Ann Edgeworth Allison, Dale L. Kirkland | 2016-09-20 |
| 9436969 | Time slice processing of tessellation and geometry shaders | Emmett M. Kilgariff, Dale L. Kirkland, Johnny S. Rhoades, Cynthia Ann Edgeworth Allison, Karim M. Abdalla | 2016-09-06 |
| 9418616 | Technique for storing shared vertices | Jerome F. Duluk, Jr., Henry Packard Moreton | 2016-08-16 |
| 9411596 | Tiled cache invalidation | Emmett M. Kilgariff | 2016-08-09 |
| 9406101 | Technique for improving the performance of a tessellation pipeline | Zhenghong Wang | 2016-08-02 |
| 9342311 | Techniques for adaptively generating bounding boxes | Pierre Souillot, Cynthia Ann Edgeworth Allison, Dale L. Kirkland, Rouslan Dimitrov | 2016-05-17 |
| 9336002 | Data structures for efficient tiled rendering | Pierre Souillot, Cynthia Ann Edgeworth Allison, Dale L. Kirkland | 2016-05-10 |
| 9311097 | Managing per-tile event count reports in a tile-based architecture | Jerome F. Duluk, Jr. | 2016-04-12 |
| 9293109 | Technique for storing shared vertices | Jerome F. Duluk, Jr., Henry Packard Moreton | 2016-03-22 |
| 9269179 | System, method, and computer program product for generating primitive specific attributes | Yury Uralsky, Tyson J. Bergland, Dale L. Kirkland, Cyril Crassin, Henry Packard Moreton | 2016-02-23 |