Issued Patents 2016
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9529400 | Automatic power domain and voltage domain assignment to system-on-chip agents and network-on-chip elements | Eric Norige, Pier Giorgio Raponi | 2016-12-27 |
| 9477280 | Specification for automatic power management of network-on-chip and system-on-chip | Anup Gangwar, Vishnu Mohan Pusuluri, Poonacha Kongetira | 2016-10-25 |
| 9471726 | System level simulation in network on chip architecture | Amit Patankar, Eric Norige | 2016-10-18 |
| 9473359 | Transactional traffic specification for network-on-chip design | Eric Norige, Pier Giorgio Raponi | 2016-10-18 |
| 9473388 | Supporting multicast in NOC interconnect | Eric Norige, Joe Rowlands, Joji Philip | 2016-10-18 |
| 9473415 | QoS in a system with end-to-end flow control and QoS aware buffer allocation | — | 2016-10-18 |
| 9444702 | System and method for visualization of NoC performance based on simulation output | Pier Giorgio Raponi, Eric Norige | 2016-09-13 |
| 9319232 | Integrated NoC for performing data communication and NoC functions | — | 2016-04-19 |
| 9294354 | Using multiple traffic profiles to design a network on chip | — | 2016-03-22 |
| 9253085 | Hierarchical asymmetric mesh with virtual routers | Eric Norige, Joji Philip, Mahmud-Ul Hassan, Sundari Mitra, Joseph B. Rowlands | 2016-02-02 |
| 9244845 | System and method for improving snoop performance | Joe Rowlands | 2016-01-26 |
| 9244880 | Automatic construction of deadlock free interconnects | Joji Philip, Eric Norige, Mahmud-Ul Hassan, Sundari Mitra | 2016-01-26 |