Issued Patents 2016
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9529400 | Automatic power domain and voltage domain assignment to system-on-chip agents and network-on-chip elements | Sailesh Kumar, Pier Giorgio Raponi | 2016-12-27 |
| 9471726 | System level simulation in network on chip architecture | Sailesh Kumar, Amit Patankar | 2016-10-18 |
| 9473359 | Transactional traffic specification for network-on-chip design | Sailesh Kumar, Pier Giorgio Raponi | 2016-10-18 |
| 9473388 | Supporting multicast in NOC interconnect | Sailesh Kumar, Joe Rowlands, Joji Philip | 2016-10-18 |
| 9444702 | System and method for visualization of NoC performance based on simulation output | Pier Giorgio Raponi, Sailesh Kumar | 2016-09-13 |
| 9253085 | Hierarchical asymmetric mesh with virtual routers | Sailesh Kumar, Joji Philip, Mahmud-Ul Hassan, Sundari Mitra, Joseph B. Rowlands | 2016-02-02 |
| 9244880 | Automatic construction of deadlock free interconnects | Joji Philip, Sailesh Kumar, Mahmud-Ul Hassan, Sundari Mitra | 2016-01-26 |