VC

Vivek Chickermane

CS Cadence Design Systems: 6 patents #1 of 202Top 1%
Overall (2016): #16,256 of 481,213Top 4%
6
Patents 2016

Issued Patents 2016

Patent #TitleCo-InventorsDate
9513335 Method for using XOR trees for physically efficient scan compression and decompression logic Steev Wilcox, Brian Foutz, Paul Alexander Cunningham, Krishna Vijaya Chakravadhanula 2016-12-06
9501590 Systems and methods for testing integrated circuit designs Paul Alexander Cunningham, Steev Wilcox 2016-11-22
9470754 Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serialization Krishna Vijaya Chakravadhanula, Brian Foutz, Steev Wilcox, Paul Alexander Cunningham, David G. Scott +2 more 2016-10-18
9470755 Method for dividing testable logic into a two-dimensional grid for physically efficient scan Brian Foutz, Steev Wilcox, Krishna Vijaya Chakravadhanula, Paul Alexander Cunningham 2016-10-18
9470756 Method for using sequential decompression logic for VLSI test in a physically efficient construction Steev Wilcox, Brian Foutz, Krishna Vijaya Chakravadhanula, Paul Alexander Cunningham 2016-10-18
9465896 Systems and methods for testing integrated circuit designs Paul Alexander Cunningham, Steev Wilcox 2016-10-11