KC

Krishna Vijaya Chakravadhanula

CS Cadence Design Systems: 4 patents #7 of 202Top 4%
📍 Vestal, NY: #4 of 42 inventorsTop 10%
🗺 New York: #1,050 of 11,723 inventorsTop 9%
Overall (2016): #39,920 of 481,213Top 9%
4
Patents 2016

Issued Patents 2016

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
9513335 Method for using XOR trees for physically efficient scan compression and decompression logic Steev Wilcox, Brian Foutz, Paul Alexander Cunningham, Vivek Chickermane 2016-12-06
9470754 Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serialization Vivek Chickermane, Brian Foutz, Steev Wilcox, Paul Alexander Cunningham, David G. Scott +2 more 2016-10-18
9470755 Method for dividing testable logic into a two-dimensional grid for physically efficient scan Brian Foutz, Steev Wilcox, Vivek Chickermane, Paul Alexander Cunningham 2016-10-18
9470756 Method for using sequential decompression logic for VLSI test in a physically efficient construction Steev Wilcox, Brian Foutz, Vivek Chickermane, Paul Alexander Cunningham 2016-10-18