| 9515155 |
E-fuse design for high-K metal-gate technology |
Roman Boschke, Maciej Wiatr, Christian Schippel |
2016-12-06 |
| 9490361 |
Canyon gate transistor and methods for its fabrication |
Thilo Scheiper |
2016-11-08 |
| 9490344 |
Methods of making transistor devices with elevated source/drain regions to accommodate consumption during metal silicide formation process |
Jan Hoentschel, Thilo Scheiper |
2016-11-08 |
| 9484407 |
Methods of forming a nanowire transistor device |
Tim Baldauf |
2016-11-01 |
| 9472642 |
Method of forming a semiconductor device structure and such a semiconductor device structure |
Jan Hoentschel, Ralf Richter, Peter Javorka |
2016-10-18 |
| 9449972 |
Ferroelectric FinFET |
Ralf Illgen, Jan Hoentschel |
2016-09-20 |
| 9443945 |
Transistor including a gate electrode extending all around one or more channel regions |
Jan Hoentschel |
2016-09-13 |
| 9431508 |
Simplified gate-first HKMG manufacturing flow |
Jan Hoentschel, Roman Boschke |
2016-08-30 |
| 9425318 |
Integrated circuits with fets having nanowires and methods of manufacturing the same |
Jan Hoentschel, Gerd Zschaetzsch |
2016-08-23 |
| 9425194 |
Transistor devices with high-k insulation layers |
Martin Gerhardt, Matthias Kessler |
2016-08-23 |
| 9412859 |
Contact geometry having a gate silicon length decoupled from a transistor length |
Ralf Richter, Peter Javorka, Jan Hoentschel |
2016-08-09 |
| 9412848 |
Methods of forming a complex GAA FET device at advanced technology nodes |
Ralf Richter, Peter Javorka, Jan Hoentschel |
2016-08-09 |
| 9401423 |
Enhancing transistor performance and reliability by incorporating deuterium into a strained capping layer |
Peter Javorka |
2016-07-26 |
| 9391176 |
Multi-gate FETs having corrugated semiconductor stacks and method of forming the same |
Jan Hoentschel, Ralf Richter, Peter Javorka |
2016-07-12 |
| 9373720 |
Three-dimensional transistor with improved channel mobility |
Jan Hoentschel, Ralf Richter, Peter Javorka |
2016-06-21 |
| 9373509 |
FINFET doping method with curvilnear trajectory implantation beam path |
Ralf Richter, Peter Javorka, Jan Hoentschel |
2016-06-21 |
| 9368513 |
Highly conformal extension doping in advanced multi-gate devices |
Gerd Zschätzsch, Dominic Thurmer |
2016-06-14 |
| 9368506 |
Integrated circuits and methods for operating integrated circuits with non-volatile memory |
Ricardo P. Mikalo |
2016-06-14 |
| 9349734 |
Selective FuSi gate formation in gate first CMOS technologies |
Peter Javorka, Gerd Zschätzsch |
2016-05-24 |
| 9343374 |
Efficient main spacer pull back process for advanced VLSI CMOS technologies |
Jan Hoentschel, Peter Javorka, Ralf Richter |
2016-05-17 |
| 9324831 |
Forming transistors without spacers and resulting devices |
Gerd Zschätzsch, Jan Hoentschel |
2016-04-26 |
| 9269714 |
Device including a transistor having a stressed channel region and method for the formation thereof |
Ralf Illgen, Gerd Zschaezsch |
2016-02-23 |
| 9257530 |
Methods of making integrated circuits and components thereof |
Gerd Zschätzsch, Jan Hoentschel |
2016-02-09 |
| 9236440 |
Sandwich silicidation for fully silicided gate formation |
Roman Boschke, Elke Erben |
2016-01-12 |
| 9231045 |
Methods for fabricating integrated circuits with polycrystalline silicon resistor structures using a replacment gate process flow, and the integrated circuits fabricated thereby |
Jan Hoentschel, Nicolas Sassiat, Ralf Richter |
2016-01-05 |
