PJ

Peter Javorka

Globalfoundries: 11 patents #49 of 2,145Top 3%
Overall (2016): #5,186 of 481,213Top 2%
11
Patents 2016

Issued Patents 2016

Patent #TitleCo-InventorsDate
9484459 Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer Stephan Kronholz, Gunda Beernink 2016-11-01
9472642 Method of forming a semiconductor device structure and such a semiconductor device structure Jan Hoentschel, Stefan Flachowsky, Ralf Richter 2016-10-18
9412859 Contact geometry having a gate silicon length decoupled from a transistor length Ralf Richter, Jan Hoentschel, Stefan Flachowsky 2016-08-09
9412848 Methods of forming a complex GAA FET device at advanced technology nodes Ralf Richter, Jan Hoentschel, Stefan Flachowsky 2016-08-09
9406565 Methods for fabricating integrated circuits with semiconductor substrate protection Ralf Richter, Jan Hoentschel 2016-08-02
9401423 Enhancing transistor performance and reliability by incorporating deuterium into a strained capping layer Stefan Flachowsky 2016-07-26
9391176 Multi-gate FETs having corrugated semiconductor stacks and method of forming the same Stefan Flachowsky, Jan Hoentschel, Ralf Richter 2016-07-12
9373720 Three-dimensional transistor with improved channel mobility Stefan Flachowsky, Jan Hoentschel, Ralf Richter 2016-06-21
9373509 FINFET doping method with curvilnear trajectory implantation beam path Ralf Richter, Stefan Flachowsky, Jan Hoentschel 2016-06-21
9349734 Selective FuSi gate formation in gate first CMOS technologies Stefan Flachowsky, Gerd Zschätzsch 2016-05-24
9343374 Efficient main spacer pull back process for advanced VLSI CMOS technologies Jan Hoentschel, Stefan Flachowsky, Ralf Richter 2016-05-17