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Methods to thin down RMG sidewall layers for scalability of gate-last planar CMOS and FinFET technology |
Yanping Shen, Min-hwa Chi, Ashish Jha |
2016-09-13 |
| 9425100 |
Methods of facilitating fabricating transistors |
Zhaoxu Shen, Min-hwa Chi, Qin Wang, Meixiong Zhao, Duohui Bei |
2016-08-23 |
| 9418899 |
Method of multi-WF for multi-Vt and thin sidewall deposition by implantation for gate-last planar CMOS and FinFET technology |
Yan Ping SHEN, Min-hwa Chi, Xusheng Wu, Weihua Tong |
2016-08-16 |
| 9379186 |
Fet structure for minimum size length/width devices for performance boost and mismatch reduction |
Qin Wang, Min-hwa Chi, Meixiong Zhao, Zhaoxu Shen, Lucas M. Salazar +1 more |
2016-06-28 |
| 9331159 |
Fabricating transistor(s) with raised active regions having angled upper surfaces |
Ashish Jha, Yan Ping SHEN, Wei Tong, Min-hwa Chi |
2016-05-03 |
| 9312145 |
Conformal nitridation of one or more fin-type transistor layers |
Wei Tong, Tien Ying Luo, Yan Ping SHEN, Feng Zhou, Jun Lian +4 more |
2016-04-12 |
| 9293580 |
Lightly doped source/drain last method for dual-epi integration |
Ka-Hing Fung, Han-Ting Tsai |
2016-03-22 |
