| 9466022 |
Hardware architecture for simulating a neural network of neurons |
Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Pallab Datta, Paul A. Merolla, Dharmendra S. Modha |
2016-10-11 |
| 9424284 |
Mapping neural dynamics of a neural model on to a coarsely grained look-up table |
Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Pallab Datta, Paul A. Merolla, Dharmendra S. Modha |
2016-08-23 |
| 9368489 |
Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array |
Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Subramanian S. Iyer, Bryan L. Jackson +3 more |
2016-06-14 |
| 9363137 |
Faulty core recovery mechanisms for a three-dimensional network on a processor array |
Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Subramanian S. Iyer, Paul A. Merolla +1 more |
2016-06-07 |
| 9244124 |
Initializing and testing integrated circuits with selectable scan chains with exclusive-or outputs |
Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more |
2016-01-26 |
