Issued Patents 2016
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9466022 | Hardware architecture for simulating a neural network of neurons | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Pallab Datta, Dharmendra S. Modha | 2016-10-11 |
| 9424284 | Mapping neural dynamics of a neural model on to a coarsely grained look-up table | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Pallab Datta, Dharmendra S. Modha | 2016-08-23 |
| 9373073 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation | John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Dharmendra S. Modha +3 more | 2016-06-21 |
| 9368489 | Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer +3 more | 2016-06-14 |
| 9363137 | Faulty core recovery mechanisms for a three-dimensional network on a processor array | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer +1 more | 2016-06-07 |
| 9269044 | Neuromorphic event-driven neural computing architecture in a scalable neural network | Filipp A. Akopyan, John V. Arthur, Rajit Manohar, Dharmendra S. Modha, Alyosha Molnar +1 more | 2016-02-23 |
| 9244124 | Initializing and testing integrated circuits with selectable scan chains with exclusive-or outputs | Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Dharmendra S. Modha +1 more | 2016-01-26 |
| 9239984 | Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network | John V. Arthur, Bernard V. Brezzo, Leland Chang, Daniel J. Friedman, Dharmendra S. Modha +3 more | 2016-01-19 |