Issued Patents 2016
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9524240 | Obscuring memory access patterns in conjunction with deadlock detection or avoidance | Shay Gueron, Gad Sheaffer | 2016-12-20 |
| 9424198 | Method, system and apparatus including logic to manage multiple memories as a unified exclusive memory | Zvika Greenfield | 2016-08-23 |
| 9411728 | Methods and apparatus for efficient communication between caches in hierarchical caching design | Ron Shalev, Yiftach Gilad, Igor Yanover, Stanislav Shwartsman, Raanan Sade | 2016-08-09 |
| 9405545 | Method and apparatus for cutting senior store latency using store prefetching | Stanislav Shwartsman, Melih Ozgul, Sebastien Hily, Raanan Sade, Ron Shalev | 2016-08-02 |
| 9348766 | Balanced P-LRU tree for a “multiple of 3” number of ways cache | Adi Basel, Gur Hildesheim, Robert S. Chappell, Ho-Seop Kim, Rohit Bhatia | 2016-05-24 |
| 9286235 | Virtual memory address range register | Gur Hildesheim, Ittai Anati, Gideon Gerzon, Uday Savagaonkar, Francis X. McKeen +3 more | 2016-03-15 |
| 9268697 | Snoop filter having centralized translation circuitry and shadow tag array | Ilan Pardo, Niranjan L. Cooray, Stanislav Shwartsman | 2016-02-23 |