Issued Patents 2016
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9348766 | Balanced P-LRU tree for a “multiple of 3” number of ways cache | Adi Basel, Gur Hildesheim, Shlomo Raikin, Robert S. Chappell, Rohit Bhatia | 2016-05-24 |
| 9292294 | Detection of memory address aliasing and violations of data dependency relationships | Muawya M. Al-Otoom, Paul Caprioli, Ryan Carlson, Omar M. Shaikh | 2016-03-22 |
| 9244827 | Store address prediction for memory disambiguation in a processing device | Robert S. Chappell, Choon Yip Soo, Srikanth Srinivasan | 2016-01-26 |