| 9507746 |
Control messaging in multislot link layer flit |
Jeff Willey, Jeffrey C. Swanson |
2016-11-29 |
| 9479196 |
High performance interconnect link layer |
Jeff Willey, Jeffrey C. Swanson, Robert J. Safranek |
2016-10-25 |
| 9444492 |
High performance interconnect link layer |
Jeff Willey, Jeffrey C. Swanson, Robert J. Safranek |
2016-09-13 |
| 9442879 |
Multiple transaction data flow control unit for high-speed interconnect |
Robert J. Safranek, Debendra Das Sharma |
2016-09-13 |
| 9442855 |
Transaction layer packet formatting |
Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman +13 more |
2016-09-13 |
| 9436605 |
Cache coherency apparatus and method minimizing memory writeback operations |
Jeffrey D. Chamberlain, Vedaraman Geetha, Yen-Cheng Liu, Adrian C. Moga, Herbert Hum +1 more |
2016-09-06 |
| 9418035 |
High performance interconnect physical layer |
Venkatraman Iyer, Darren S. Jue, Fulvio Spagna, Ashish Gupta |
2016-08-16 |
| 9418009 |
Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory |
Adrian C. Moga, Vedaraman Geetha, Bahaa Fahim, Yen-Cheng Liu, Jeffrey D. Chamberlain +1 more |
2016-08-16 |
| 9405687 |
Method, apparatus and system for handling cache misses in a processor |
Bahaa Fahim, Samuel D. Strom, Vedaraman Geetha, Yen-Cheng Liu, Krishnakumar Ganapathy +1 more |
2016-08-02 |
| 9355058 |
High performance interconnect physical layer |
Venkatraman Iyer, Darren S. Jue, Fulvio Spagna, Debendra Das Sharma, Jeffrey C. Swanson |
2016-05-31 |
| 9336175 |
Utilization-aware low-overhead link-width modulation for power reduction in interconnects |
Ankush Varma, Buck Gremel, Krishnakanth V. Sistla, Michael Cole |
2016-05-10 |
| 9280507 |
High performance interconnect physical layer |
Venkatraman Iyer, Darren S. Jue, Jeff Willey |
2016-03-08 |
| 9235520 |
Protocol for conflicting memory transactions |
Manoj K. Arora, Rahul Pal, Dheemanth Nagaraj |
2016-01-12 |
| 9229897 |
Embedded control channel for high speed serial interconnect |
Venkatraman Iyer, Debendra Das Sharma, Darren S. Jue |
2016-01-05 |