Issued Patents 2016
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9530740 | 3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach | Mark Bohr, Andrew W. Yeoh, Christopher M. Pelto, Hiten Kothari, Seshu V. Sattiraju +1 more | 2016-12-27 |
| 9489354 | Masking content while preserving layout of a webpage | Michael W. Nail, Homan Lee | 2016-11-08 |
| 9449913 | 3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias | Mark Bohr, Andrew W. Yeoh, Christopher M. Pelto, Hiten Kothari, Seshu V. Sattiraju +1 more | 2016-09-20 |
| 9252111 | Method for handling very thin device wafers | — | 2016-02-02 |