Issued Patents 2016
Showing 1–25 of 164 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9524205 | Code fingerprint-based processor malfunction detection | Giles R. Frazier, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum | 2016-12-20 |
| 9524196 | Adaptive process for data sharing with selection of lock elision and locking | Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2016-12-20 |
| 9524100 | Page table including data fetch width indicator | Jose E. Moreira, Balaram Sinharoy | 2016-12-20 |
| 9524188 | Multithreaded transactions | Fadi Y. Busaba, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum | 2016-12-20 |
| 9524187 | Executing instruction with threshold indicating nearing of completion of transaction | Jonathan D. Bradbury, Dan F. Greiner, Maged M. Michael, Chung-Lung K. Shum | 2016-12-20 |
| 9524257 | Transactional execution enabled supervisor call interruption while in TX mode | Jonathan D. Bradbury, Dan F. Greiner, Chung-Lung K. Shum | 2016-12-20 |
| 9524195 | Adaptive process for data sharing with selection of lock elision and locking | Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2016-12-20 |
| 9514301 | Interlinking modules with differing protections using stack indicators | — | 2016-12-06 |
| 9513916 | Instruction merging optimization | Valentina Salapura | 2016-12-06 |
| 9514006 | Transaction tracking within a microprocessor | Fadi Y. Busaba, Eric M. Schwarz | 2016-12-06 |
| 9513805 | Page table including data fetch width indicator | Jose E. Moreira, Balaram Sinharoy | 2016-12-06 |
| 9513924 | Predictor data structure for use in pipelined processing | Valentina Salapura | 2016-12-06 |
| 9513915 | Instruction merging optimization | Valentina Salapura | 2016-12-06 |
| 9507595 | Execution of multi-byte memory access instruction specifying endian mode that overrides current global endian mode | Brett Olsson | 2016-11-29 |
| 9507717 | Multithreaded transactions | Fadi Y. Busaba, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum | 2016-11-29 |
| 9507628 | Memory access request for a memory protocol | Fadi Y. Busaba, Harold W. Cain, III, Valentina Salapura, Timothy J. Slegel | 2016-11-29 |
| 9501232 | Transactional memory operations with write-only atomicity | Chung-Lung K. Shum, Timothy J. Slegel | 2016-11-22 |
| 9495237 | Detection of corruption of call stacks | Ronald I. McIntosh | 2016-11-15 |
| 9495138 | Scheme for verifying the effects of program optimizations | Giles R. Frazier, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum | 2016-11-15 |
| 9495157 | Fingerprint-based branch prediction | Jonathan D. Bradbury, Giles R. Frazier, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum | 2016-11-15 |
| 9495108 | Transactional memory operations with write-only atomicity | Chung-Lung K. Shum, Timothy J. Slegel | 2016-11-15 |
| 9495202 | Transaction digest generation during nested transactional execution | Valentina Salapura | 2016-11-15 |
| 9495306 | Dynamic management of a processor state with transient cache memory | Jonathan D. Bradbury, Dan F. Greiner, Christian Jacobi, Younes Manton, Anthony Saporito +3 more | 2016-11-15 |
| 9489142 | Transactional memory operations with read-only atomicity | Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel | 2016-11-08 |
| 9489229 | Transparent dynamic code optimization | — | 2016-11-08 |