Issued Patents 2016
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9519747 | Dynamic and adaptive timing sensitivity during static timing analysis using look-up table | Nathan C. Buck, Brian M. Dreibelbis, John P. Dubuque, Eric A. Foreman, David J. Hathaway +6 more | 2016-12-13 |
| 9501609 | Selection of corners and/or margins using statistical static timing analysis of an integrated circuit | Eric A. Foreman, Jeffrey G. Hemmett, Gregory M. Schaeffer, Stephen G. Shurma, Alexander J. Suess +3 more | 2016-11-22 |
| 9495218 | Efficient parallel processing of a network with conflict constraints between nodes | Hemlata Gupta, David J. Hathaway, Ronald D. Rose | 2016-11-15 |
| 9495497 | Dynamic voltage frequency scaling | Nathan C. Buck, Eric A. Foreman, Jeffrey G. Hemmett, Gregory M. Schaeffer, Stephen G. Shuma +4 more | 2016-11-15 |
| 9483604 | Variable accuracy parameter modeling in statistical timing | Eric A. Foreman, Jeffrey G. Hemmett, Gregory M. Schaeffer, Stephen G. Shuma, Alexander J. Suess +2 more | 2016-11-01 |
| 9430603 | Scaling voltages in relation to die location | Eric A. Foreman, Nazmul Habib | 2016-08-30 |
| 9418201 | Integration of functional analysis and common path pessimism removal in static timing analysis | Peter C. Elmendorf, Stephen G. Shuma, Alexander J. Suess | 2016-08-16 |
| 9400864 | System and method for maintaining slack continuity in incremental statistical timing analysis | David J. Hathaway, Jeffrey G. Hemmett, Debjit Sinha | 2016-07-26 |
| 9342639 | Method of hierarchical timing closure of VLSI circuits using partially disruptive feedback assertions | Christine T. Casey, Ravichander Ledalla, Debjit Sinha | 2016-05-17 |
| 9280624 | System and method for efficient statistical timing analysis of cycle time independent tests | David J. Hathaway, Stephen G. Shuma, Chandramouli Visweswariah | 2016-03-08 |