Issued Patents 2016
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9342639 | Method of hierarchical timing closure of VLSI circuits using partially disruptive feedback assertions | Kerim Kalafala, Ravichander Ledalla, Debjit Sinha | 2016-05-17 |
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9342639 | Method of hierarchical timing closure of VLSI circuits using partially disruptive feedback assertions | Kerim Kalafala, Ravichander Ledalla, Debjit Sinha | 2016-05-17 |