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Peter Wung Lee — 13 Patents in 2016

Disney: 5 patents #71 of 1,389Top 6%

ATAplus Flash Technology: 3 patents #1 of 1Top 100%

UNUnknown: 2 patents #94 of 3,294Top 3%

Saratoga, CA: #14 of 660 inventorsTop 3%

California: #604 of 57,791 inventorsTop 2%

Overall (2016): #3,627 of 481,213Top 1%

13 Patents 2016

Issued Patents 2016

Showing 1–13 of 13 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
9530492	NAND array hiarchical BL structures for multiple-WL and All-BL simultaneous erase, erase-verify, program, program-verify, and read operations	—	2016-12-27
9524773	Multi-task concurrent/pipeline NAND operations on all planes	—	2016-12-20
9490427	Resistive random access memory cell structure	Pantas Sutardja, Albert Wu, Winston Lee, Runzi Chang	2016-11-08	$3,471,000
9443579	VSL-based VT-compensation and analog program scheme for NAND array without CSL	—	2016-09-13
9443578	NAND array architecture for multiple simultaneous program and read	—	2016-09-13
9437306	NAND array architecture for multiple simutaneous program and read	—	2016-09-06
9424911	Method and apparatus for screening memory cells for disturb failures	Winston Lee, Moon-Hae Son	2016-08-23	$5,624,000
9324417	Systems and methods for avoiding read disturbance in a static random-access memory (SRAM)	Winston Lee	2016-04-26	$2,697,000
9293205	Multi-task concurrent/pipeline NAND operations on all planes	—	2016-03-22
9275731	Systems and methods for increasing the read sensitivity of a resistive random access memory (RRAM)	Pantas Sutardja, Albert Wu, Runzi Chang, Winston Lee	2016-03-01	$2,781,000
9263137	NAND array architecture for multiple simutaneous program and read	—	2016-02-16
9245961	Reducing source contact to gate spacing to decrease transistor pitch	Albert Wu, Pantas Sutardja, Winston Lee, Chien-Chuan Wei, Runzi Chang	2016-01-26	$1,496,000
9230677	NAND array hiarchical BL structures for multiple-WL and all-BL simultaneous erase, erase-verify, program, program-verify, and read operations	—	2016-01-05