Issued Patents 2011
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7990786 | Read-leveling implementations for DDR3 applications on an FPGA | Michael H. M. Chu, Joseph Huang, Chiakang Sung, Andrew Bellis, Philip Clarke +1 more | 2011-08-02 |
| 7990783 | Postamble timing for DDR memories | Philip Clarke, Andrew Bellis, Joseph Huang, Michael H. M. Chu | 2011-08-02 |
| 7983094 | PVT compensated auto-calibration scheme for DDR3 | Manoj B. Roge, Andrew Bellis, Philip Clarke, Joseph Huang, Michael H. M. Chu | 2011-07-19 |
| 7969215 | High-performance memory interface circuit architecture | Joseph Huang, Chiakang Sung, Philip Pan, Andy L. Lee, Brian Johnson | 2011-06-28 |
| 7928770 | I/O block for high performance memory interfaces | Andrew Bellis, Philip Clarke, Joseph Huang, Michael H. M. Chu, Manoj B. Roge | 2011-04-19 |
| 7898296 | Distribution and synchronization of a divided clock signal | Ning Xue, Philip Clarke, Joseph Huang | 2011-03-01 |
| 7893739 | Techniques for providing multiple delay paths in a delay circuit | Pradeep Nagarajan, Chiakang Sung, Joseph Huang | 2011-02-22 |
| 7884619 | Method and apparatus for minimizing skew between signals | Joseph Huang, Chiakang Sung, Eric Choong-Yin Chang, Peter Boyle, Adam Wright | 2011-02-08 |
| 7876630 | Postamble timing for DDR memories | Philip Clarke, Andrew Bellis, Joseph Huang, Michael H. M. Chu | 2011-01-25 |