Issued Patents 2011
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8081483 | USB flash disk | — | 2011-12-20 |
| 8029299 | Cover unit | — | 2011-10-04 |
| 7990786 | Read-leveling implementations for DDR3 applications on an FPGA | Michael H. M. Chu, Chiakang Sung, Yan Chong, Andrew Bellis, Philip Clarke +1 more | 2011-08-02 |
| 7990783 | Postamble timing for DDR memories | Philip Clarke, Andrew Bellis, Yan Chong, Michael H. M. Chu | 2011-08-02 |
| 7983094 | PVT compensated auto-calibration scheme for DDR3 | Manoj B. Roge, Andrew Bellis, Philip Clarke, Michael H. M. Chu, Yan Chong | 2011-07-19 |
| 7969215 | High-performance memory interface circuit architecture | Chiakang Sung, Philip Pan, Yan Chong, Andy L. Lee, Brian Johnson | 2011-06-28 |
| D640263 | USB memory stick | — | 2011-06-21 |
| 7926617 | Quick oil change apparatus and process | Frances E. Lockwood, Timothy L. Caudill | 2011-04-19 |
| 7928770 | I/O block for high performance memory interfaces | Andrew Bellis, Philip Clarke, Yan Chong, Michael H. M. Chu, Manoj B. Roge | 2011-04-19 |
| 7898296 | Distribution and synchronization of a divided clock signal | Ning Xue, Philip Clarke, Yan Chong | 2011-03-01 |
| 7893739 | Techniques for providing multiple delay paths in a delay circuit | Pradeep Nagarajan, Yan Chong, Chiakang Sung | 2011-02-22 |
| 7884619 | Method and apparatus for minimizing skew between signals | Yan Chong, Chiakang Sung, Eric Choong-Yin Chang, Peter Boyle, Adam Wright | 2011-02-08 |
| 7876630 | Postamble timing for DDR memories | Philip Clarke, Andrew Bellis, Yan Chong, Michael H. M. Chu | 2011-01-25 |
| 7871570 | Fluidic array devices and systems, and related methods of use and manufacturing | Yong Shi, Yufeng Ma | 2011-01-18 |