Issued Patents 2011
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7990783 | Postamble timing for DDR memories | Andrew Bellis, Yan Chong, Joseph Huang, Michael H. M. Chu | 2011-08-02 |
| 7990786 | Read-leveling implementations for DDR3 applications on an FPGA | Michael H. M. Chu, Joseph Huang, Chiakang Sung, Yan Chong, Andrew Bellis +1 more | 2011-08-02 |
| 7983094 | PVT compensated auto-calibration scheme for DDR3 | Manoj B. Roge, Andrew Bellis, Joseph Huang, Michael H. M. Chu, Yan Chong | 2011-07-19 |
| 7928770 | I/O block for high performance memory interfaces | Andrew Bellis, Joseph Huang, Yan Chong, Michael H. M. Chu, Manoj B. Roge | 2011-04-19 |
| 7898296 | Distribution and synchronization of a divided clock signal | Ning Xue, Joseph Huang, Yan Chong | 2011-03-01 |
| 7876630 | Postamble timing for DDR memories | Andrew Bellis, Yan Chong, Joseph Huang, Michael H. M. Chu | 2011-01-25 |