Issued Patents 2011
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8086783 | High availability memory system | James A. O'Connor, Kevin C. Gower, Warren E. Maule | 2011-12-27 |
| 8055976 | System and method for providing error correction and detection in a memory system | Kyu-hyoun Kim, Paul W. Coteus | 2011-11-08 |
| 8041989 | System and method for providing a high fault tolerant memory system | James A. O'Connor, Luiz C. Alves, William J. Clarke, Timothy J. Dell, Thomas J. Dewkett +1 more | 2011-10-18 |
| 8041990 | System and method for error correction and detection in a memory system | James A. O'Connor, Luis C. Alves, William J. Clarke, Timothy J. Dell, Thomas J. Dewkett +1 more | 2011-10-18 |
| 8023345 | Iteratively writing contents to memory locations using a statistical model | Matthew J. Breitwisch, Roger W. Cheek, Stefanie Chiras, Ibrahim M. Elfadel, Michele M. Franceschini +3 more | 2011-09-20 |
| 8024642 | System and method for providing constrained transmission and storage in a random access memory | — | 2011-09-20 |
| 8004884 | Iterative write pausing techniques to improve read latency of memory systems | Michele M. Franceschini, Moinuddin K. Qureshi, Vijayalakshmi Srinivasan | 2011-08-23 |
| 7984329 | System and method for providing DRAM device-level repair via address remappings external to the device | Darren L. Anand, Jeffrey H. Dreibelbis, Charles A. Kilmer, Warren E. Maule, Robert B. Tremaine | 2011-07-19 |
| 7962700 | Systems and methods for reducing latency for accessing compressed memory using stratified compressed memory architectures and organization | Peter A. Franaszek, Robert B. Tremaine | 2011-06-14 |
| 7949931 | Systems and methods for error detection in a memory system | — | 2011-05-24 |
| 7895502 | Error control coding methods for memories with subline accesses | Junsheng Han, Michael R. Trombley | 2011-02-22 |