UG

Udayan Gumaste

CS Cadence Design Systems: 2 patents #27 of 259Top 15%
📍 San Jose, CA: #856 of 4,297 inventorsTop 20%
🗺 California: #7,487 of 41,698 inventorsTop 20%
Overall (2011): #60,234 of 364,097Top 20%
2
Patents 2011

Issued Patents 2011

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
7984399 System and method for random defect yield simulation of chip with built-in redundancy Roland Ruehl, Mathew Koshy, Jonathan R. Fales 2011-07-19
7886243 System and method for using rules-based analysis to enhance models-based analysis Roland Ruehl, Mathew Koshy, Harsh Deshmane 2011-02-08