JF

Jonathan R. Fales

CS Cadence Design Systems: 1 patents #62 of 259Top 25%
📍 South Burlington, VT: #84 of 184 inventorsTop 50%
🗺 Vermont: #269 of 615 inventorsTop 45%
Overall (2011): #262,860 of 364,097Top 75%
1
Patents 2011

Issued Patents 2011

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
7984399 System and method for random defect yield simulation of chip with built-in redundancy Roland Ruehl, Mathew Koshy, Udayan Gumaste 2011-07-19