Issued Patents 2011
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8067314 | Gate trim process using either wet etch or dry etch approach to target CD for selected transistors | Bradley Marc Davis, Jihwan P. Choi | 2011-11-29 |
| 8035153 | Self-aligned patterning method by using non-conformal film and etch for flash memory and other semiconductor applications | Shenqing Fang, Jihwan P. Choi, Calvin T. Gabriel, Fei Wang, Alexander H. Nickel +4 more | 2011-10-11 |
| 8022468 | Ultraviolet radiation blocking interlayer dielectric | Minh Van Ngo, Wenmei Li, Jeffrey A. Shields, Ning Cheng, Cinti X. Chen | 2011-09-20 |
| 8012830 | ORO and ORPRO with bit line trench to suppress transport program disturb | Ning Cheng, Kuo-Tung Chang, Hiro Kinoshita, Chih-Yuh Yang, Lei Xue +3 more | 2011-09-06 |
| 7985687 | System and method for improving reliability in a semiconductor device | Hiroyuki Kinoshita, Unsoon Kim, Harpreet Sachar | 2011-07-26 |
| 7977797 | Integrated circuit with contact region and multiple etch stop insulation layer | Wenmei Li, Dawn Hopper, Kouros Ghandehari | 2011-07-12 |
| 7972951 | Memory device etch methods | Jihwan P. Choi | 2011-07-05 |
| 7951675 | SI trench between bitline HDP for BVDSS improvement | Lei Xue, Aimin Xing, Chih-Yuh Yang, Chungho Lee | 2011-05-31 |
| 7927723 | Film stacks to prevent UV-induced device damage | Ning Cheng, Minh Van Ngo, Hirokazu Tokuno, Wenmei Li | 2011-04-19 |
| 7906807 | Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics | Ning Cheng, Calvin T. Gabriel, Lei Xue, Harpreet Sachar, Phillip Jones +3 more | 2011-03-15 |