Issued Patents 2005
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6979615 | System and method for forming a semiconductor with an analog capacitor using fewer structure steps | Louis N. Hutter, James Todd, Jozef Mitros, William Nehrer | 2005-12-27 |
| 6958269 | Memory device with reduced cell size | Josef Czeslaw Mitros, Lily Springer | 2005-10-25 |
| 6939770 | Method of fabricating semiconductor device having triple LDD structure and lower gate resistance formed with a single implant process | Jianshi Wang, Yue-Song He, Jun-Kyu Kang | 2005-09-06 |
| 6930005 | Low cost fabrication method for high voltage, high drain current MOS transistor | Taylor R. Efland, Jozef Mitros | 2005-08-16 |
| 6885054 | Threshold voltage stabilizer, method of manufacturing and integrated circuit employing the same | Xiaoju Wu, Pinghai Hao | 2005-04-26 |
| 6873021 | MOS transistors having higher drain current without reduced breakdown voltage | Jozef Mitros, Taylor R. Efland | 2005-03-29 |
| 6861303 | JFET structure for integrated circuit and fabrication method | Pinghai Hao, Fan-Chi Hou | 2005-03-01 |